Synchronous digital systems, including memory, rely on one or more clock signals to synchronize elements across the system. Typically, one or more clock signals are distributed across the system on one or more clock lines. However, due to variations in the width and height of metal lines, the rising edges of a clock signal in different parts of the system are not always synchronized. The time difference between a rising or falling edge in one part of the system with the corresponding rising or falling edge in another part of the system is referred to as “timing skew” or “clock skew.” In double data rate memory, timing skew is very important.
Furthermore, when the chip density becomes larger, routing metal lines are run longer distances which creates more opportunities for larger skew.
Clock skew causes digital systems to malfunction. For example, it is common for circuits in digital systems to have a first flip-flop output driving a second flip-flop input. With a synchronized clock on the clock input of both flip-flops, the data in the first flip-flop is successfully clocked into the second flip-flop. However, if the active edge on the second flip flop is delayed by clock skew, the second flip-flop might not capture the data from the first flip-flop before the first flip-flop changes state.
Delay lock loops are used in digital systems to minimize clock skew. Delay lock loops typically use delay elements to synchronize the active edges of a reference clock signal in one part of the system with a feedback clock signal from a second part of the system.
FIG. 1A illustrates a block diagram of a delayed lock loop of the prior art. A reference clock signal 100 is received at an input buffer 102. The input buffer 102 stores data signals including the clock signal 100 temporarily. After a time t, the input buffer sends the data to delay cells 104 and a charge pump/phase detector 106. The delay cells 104 delay input clock signals as needed. The charge pump/phase detector 106 compares the phase of a local oscillator (not shown) with the reference clock signal 100. The charge pump/phase detector 106 also ensures that the local oscillator (not shown) stays in the same frequency as the reference clock signal 100 by delivering positive or negative charge pulses depending on whether the reference clock signal 100 leads or lags the local oscillator (not shown). The delay cells 104 and the charge pump/phase detector 106 function together to ensure the signals have the correct phase and frequency. A driver 108 then receives the modified signals and drives the signals to the respective output lines C—0 110, C—90 112, C—180 114 and C—270 116. Since there are four separate output lines corresponding to each phase signal and each line could have varying dimensions, it is possible for there to be a skew 118 in the data signals.
FIG. 1B illustrates a timing diagram of the prior art. As is shown, there are four separate signals with different phases: 0 degree, 90 degree, 180 degree and 270 degree. Since the signals are on their own respective wires, it is possible for skewing 118 to occur as denoted by the left and right arrows.
FIG. 2 illustrates an example of an internal view of a memory in a center aligned scheme. Within the memory is a delayed lock loop 200. As described above, the delayed lock loop functions to maintain a phase for the different signals and then sends the signals to their respective lines, 110, 112, 114 and 116 (FIG. 1A). The lines 110, 112, 114 and 116 (FIG. 1A) are bundled as cables 202. Each cable goes to a respective receiver 204. The concern of skewing remains since within each cable 204 the separate metal lines have differing thickness which results in skewing of the data.